1. Field of the Invention
The present invention relates to a so-called DELTA (DEpleted Lean channel TrAnsistor) semiconductor device and a method of fabricating the same.
2. Description of the Related Art
A so-called DELTA semiconductor element has attracted attention as a semiconductor element meeting demands for a finer diffusion layer and a higher integration degree in recent years. This semiconductor element has an SOI structure in which a pillar projecting semiconductor layer is formed on a semiconductor substrate via an insulating layer for element isolation, a gate electrode is formed to cover a central portion of this semiconductor layer via a gate insulating film, and a source and a drain are formed in the semiconductor layer on the two sides of the gate electrode. A channel between the source and the drain is depleted to achieve high drivability.
More specifically, Japanese Patent Laid-Open No. 6-310595 has disclosed a method of forming an element isolation region above a semiconductor substrate including a pillar projection by ion-implanting oxygen into the semiconductor substrate.
Also, Japanese Patent Laid-Open No. 5-198817 or 4-294585 has disclosed a structure in which a gate electrode is so formed as to bury upper and lower portions of a pillar projection or a trench and a source and a drain are formed on the bottom of the trench.
Furthermore, as one example of semiconductor devices similar to the DELTA semiconductor device, Japanese Patent Laid-Open No. 1-248557 has disclosed a semiconductor device in which a gate electrode is so formed as to surround the side surfaces of a pillar projection formed on a semiconductor substrate, diffusion regions serving as a source and a drain are formed on the upper surface of the pillar projection and in the semiconductor substrate around the pillar projection, and a capacitor is so formed as to be connected to the diffusion region on the upper surface of the pillar projection.
In the semiconductor device disclosed in Japanese Patent Laid-Open No. 6-310595, however, an element isolation insulating film must be formed on a semiconductor substrate, although the film is not a thick oxide film such as a field oxide film formed by a LOCOS process. This unavoidably complicates the fabrication process.
In the semiconductor device disclosed in Japanese Patent Laid-Open No. 5-198817 or 4-294585, only a source and a drain are formed in upper and lower portions of a pillar projection formed on a semiconductor substrate. That is, this device structure does not meet demands for multiple channels in recent years.
In the semiconductor device disclosed in Japanese Patent Laid-Open No. 1-248557, a gate electrode is so formed as to cover the side surfaces of a pillar projection by anisotropic etching. Therefore, it is impossible to make the film thickness and the shape of the gate electrode uniform. Consequently, the shape of the gate electrode becomes very difficult to control as the dimensions of an element are further decreased.